In the field of computing platforms, a software application may be originally written to be executed by a first computing platform, for example, a 32-bit based computing platform, e.g., Intel (RTM) Architecture 32 (IA-32). In some cases, it may be possible to execute the software application on a second computing platform, for example, a 64-bit based computing platform, e.g., Intel (RTM) Itanium (RTM) processor, using suitable hardware and/or software to translate and execute the software application.
During translation or execution of the software application on the second computing platform misaligned data access and problems associated with data misalignment may occur. Data misalignment may include, for example, a data item residing at a memory address that may not be efficiently accessed by a processor. Undesired overhead, e.g., additional processing cycles or processing time, may be required when the second computing platform attempts to accesses a misaligned data item. In some cases, execution of a software application on the second computing platform may compound and intensify existing performance problems, e.g., due to data misalignment, that are also experienced when the software application is executed by the first (i.e., the original) computing platform. This may significantly decrease performance speed and may significantly increase processing time and/or the number of processing cycles. Furthermore, in some cases, a misaligned data access event may be treated as an error by an application or by an operating system, e.g., running on the second computing platform, as an error, and may consequently cause early termination of an application or other undesired results.
Data misalignment access problems may be partially mitigated using a relatively long code sequence to replace each instruction that may result in a misaligned data access event. However, bulk application of such long code sequences to prevent all data misalignment access problems may be inefficient and may incur significant overhead, e.g., additional processing cycles and/or processing time.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements.